The present invention is directed generally to data processing apparatus, and particularly to a novel protocol that permits distributed arbitration for access to a processor system synchronous bus, and efficient information transfer on the system bus.
In a data processing system, information is most likely to be transferred among the various elements (e.g., memory, input-out channels, and the like) of the system by a processor bus, that may be either synchronous or asynchronous, according to predetermined protocols. For high speed information transfers it is often preferred that a synchronous bus be used in which a periodic clock signal is used to define the incremental time periods within which units of information are passed on the system bus from a sender to a receiver unit. While there are a variety of synchronous bus protocols in use, most if not all have certain undesirable features. For example, one such bus protocol relies upon a master control unit that maintains a central arbitration scheme for bus access. Such protocols tend to be wasteful in time, expensive in circuit elements and their count, and complex in design. Other protocols for information transfers on a synchronous bus permit transfers only in bursts of specified length. Thus, large quantities of information must be broken into smaller portions and transmitted at the expense of time and circuit complexity.
Often, too, it is a fact that default devices are not given fair (e.g., equal) access to the bus for information transfers; the default device must accede to other devices before it can gain access. Alternatively, the default device can be included in a prioritization scheme at the cost, again, of circuitry and system complexity.
Yet another feature believed undesirable is that high speed transfers often do not "handshake" the individual units of a large transfer; that is, the entire transfer is made before any signalling is asserted to indicate whether or not an error in transmission has occurred.